There are four basic operations in semiconductor processing, layering, patterning, doping, and heat treatments. Layering is the operation used to add thin layers to the surface of a semiconductor wafer. Patterning is the series of steps that results in the removal of selected portions of the layers added in layering. Doping is the process that puts specific amounts of dopants in the wafer surface through openings in the surface layers. Finally, heat treatments are the operations in which the wafer is heated and cooled to achieve specific results, where no additional material is added or removed from the wafer.
Of these four basic operations, patterning is typically the most critical. The patterning operation creates the surface parts of the devices that make up a circuit on the semiconductor wafer. The operation sets the critical dimensions of these devices. Errors during patterning can cause distorted or misplaced defects that result in changes in the electrical function of the device, as well as device defects.
The patterning process is also known by the terms photomasking, masking, photolithography, and microlithography. The process is a multi-step process similar to photography or stenciling. The required pattern is first formed in photomasks and transferred into the surface layers of the semiconductor wafer. A mask is precisely aligned over the wafer and the photoresist. This causes the exposure of the photoresist, except for the part that was masked by the photomask. The unexposed photoresist is then removed.
A given photomask may have a number of dies of the same semiconductor layout or design, or may have a number of dies of different layouts of design. However, regardless of the number or type of dies on a photomask, generally for a given photomask all the dies are for performing the same functionality. For instance, all the dies on the mask may relate to being an oxide deposition mask, a polysilicon mask, an implant mask, and so on.
FIGS. 1A-1C show sample masks according to the prior art that illustrate this limitation. In FIG. 1A, the photomask 100 has separate dies 102, 104, 106, and 108. The dies 102, 104, 106, and 108 may be for the same semiconductor device or for different semiconductor devices. However, all of the dies 102, 104, 106, and 108 relate to performing lithography with respect to the same functionality, specifically with respect to polysilicon. Similarly, in FIG. 1B, the photomask 150 has separate dies 152, 154, 156, and 158, which may be for the same semiconductor device or for different semiconductor devices. Again, however, all of the dies 152, 154, 156, and 158 relate to performing lithography with respect to the same functionality, specifically with respect to oxide deposition (OD). Finally, in FIG. 1C, the dies of the photomask 170 relate to performing lithography with respect to the same functionality, specifically with respect to via holes, or “vias,” as to the same metallization layer, metallic layer one.
Moreover, since the invention of the integrated circuit (IC), semiconductor chip features have become exponentially smaller and the number of transistors per device exponentially larger. Advanced IC's with hundreds of millions of transistors at feature sizes of 0.13 micron, 0.10 micron, and less are becoming routine. Improvement in overlay tolerances in optical photolithography, and the introduction of new light sources with progressively shorter wavelengths, have allowed optical steppers to significantly reduce the resolution limit for semiconductor fabrication far beyond one micron.
The reduction in feature size makes for fabrication photomasks a more difficult and expensive process. The cost of making such masks, in fact, can become a significant problem in product and technology development of semiconductor fabrication. In particular, because there usually must be one mask for each type of semiconductor operation or functionality to be performed, a great number of masks may have to be manufactured to completely fabricate a desired semiconductor device, which adds to the fabrication cost of the semiconductor device.
Therefore, there is a need for reducing the number of masks needed to fabricate one or more desired semiconductor devices. Such mask reduction should be able to be employed in conjunction with devices having small feature sizes. For these and other reasons, there is a need for the present invention.